1. Field of the Invention
The present invention relates to a data transferring device and method in an asynchronous transfer mode switch and, more specifically, to a device for dualizing main processors and transferring data from an active main processor to a standby main processor.
2. Description of the Related Art
FIG. 1 is a diagram showing the construction of an asynchronous transfer mode switch. As depicted in FIG. 1, an asynchronous transfer mode switch (ATM) includes local subsystems 10 connected with a subscriber and a trunk, and a central subsystem 22 for switching ATM cells of local subsystems 10.
Further, each local subsystem 10 is constructed with a subscriber interface module (SIM) 12 for interfacing with the subscriber, a trunk interface module (IM) 13 for interfacing with the trunk, a local switch 14 for switching-outputting cells of SIM 12 and TIM 13, and a main processor 11 for controlling local switch 14 and overall operations of the corresponding local subsystem.
Furthermore, central subsystem 22 is comprised of a central switch 20 and main processor 21, central switch 20 is connected with each local subsystem 10 and the switching-outputting the cells of the local subsystems 10, and main processor 21 controls overall operations of central switch 20.
Because transferring the cells by using the asynchronous transfer mode, the ATM switch having the construction as mentioned previously, has its communication system different from that of a general line switch and thus, main processors 11 and 21 have the construction very different from the above general line switch. In general, main processors 11 and 21, used for local subsystems 10 and the central subsystem 22, are operated with a single construction as shown in FIG. 2 by adhering a main board to a work station. Herein, the above main processors will be explained with being assumed to be a sun work station and a product of SUN MICROSYSTEMS CO., LTD.
FIG. 2 is a block diagram showing the construction of a main processor in a conventional asynchronous transfer mode switch having the construction of FIG. 1.
With respect to the construction of the main processor having the construction of FIG. 2, a main controller 212 is a microprocessor for controlling the overall operations of the work station annd can be replaced with a SuperSPARC CPU. A cache controller 214 is connected with an MBUS 251 and controls its function of interfacing data between an E-cache (External cache) 216 and MBUS 251 under the control of main controller 212. A memory controller 220 is coupled with MBUS 251 and controls the data interfacing function between MBUS 251 and a memory 218.
An M bus to S bus interface (MSI) 222 performs its interfacing function between MBUS 251 and an SBUS 253. A SEC (S bus to External bus Controller) 224 performs its function of matching the SBUS 253 and a low speed external EPROM, NVRAM, Serial controller and etc. A MACIO (MAster I/O controller) 226 performs its function of being matched with the SBUS 253 and, SCSI, Ethernet, and etc.
Then, MBUS 251 as a SPARC internal standard bus, corresponds to a 64 bit bus for communicating the processor and memory controller 220. SBUS 253 is connected with MBUS 251 by MSI 222, which corresponds to a 32 bit bus for being matched with SCSI, Ethernet, EPROM, Serial controller, etc.
I have determined that when using the main processor of the single construction as explained above, once the processor is down, the operation of the corresponding subsystem is terminated. For this reason, there is a problem in that the service of the switch can be stopped resultedly. In order to solve the foregoing problem, the main processors of local subsystem 10 and central subsystem 22 are designed with having the dualization construction, and the main processor of the dualization construction transfers the data processed by the active processor to the standby processor, so that two processors can have the same data as each other, according to the principles of the present invention.